参数资料
| 型号： | ISL6353CRTZ |
| 厂商： | Intersil |
| 文件页数： | 5/30页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR VR12 40TQFN |
| 标准包装： | 60 |
| 应用： | 控制器，DDR，Intel VR12 |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
ISL6353
Pin Descriptions (Continued)
PIN NUMBER
17
18, 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
-
SYMBOL
RTN
ISUMN and ISUMP
VDD
VIN
PROG1
BOOT1
UG1
PH1
GND
LG1
PWM3
VDDP
LG2
GND
PH2
UG2
BOOT2
PROG2
PSI
VSET2
VSET1
OVP
ADDR
GND (Bottom Pad)
5
DESCRIPTION
Output voltage sense return pin. Connect to the ground at desired remote sensing location.
Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.
5V bias power.
Input supply voltage, used for input supply feed-forward compensation.
The program pin for the voltage regulator I MAX setting. Refer to Table 6.
Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT1 pin.
Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side
MOSFET.
Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side
MOSFET.
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other
phases to operate.
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1μF using an
MLCC capacitor to the ground plane close to the IC.
Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side
MOSFET.
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side
MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT2 pin.
The program pin for the voltage regulator V BOOT voltage, droop enable/disable and the number of active phases
for PS1 mode.
This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to
ground, the controller will refer only to the power state indicated by the serial communication bus register. If the
pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,
the controller will enter the PS2 state.
This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator
with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to
the VID setting indicated by the serial communication bus register.
This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator
with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the
VID setting indicated by the serial communication bus register.
An inverter output, latched high for an overvoltage event. It is reset by POR.
This pin sets the address offset register, range from 0 to 13 (0h to Dh).
Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground
pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground
planes in PCB internal layers.
September 15, 2011
FN6897.0
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