参数资料
型号: ISL6323BCRZ
厂商: Intersil
文件页数: 1/36页
文件大小: 0K
描述: IC PWM CTRLR SYNC BUCK DL 48QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
?
ISL6323B
Data Sheet
May 12, 2010
FN6879.1
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6323B dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323B supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323B features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a two-to-four-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multi-phase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323B features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient
response to load apply and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6323B supports Power Savings Mode by dropping
the number of phases to two when the PSI_L bit is set.
Ordering Information
TEMP.
Features
? Processor Core Voltage Via Integrated Multi-Phase
Power Conversion
? Configuration Flexibility
- 1- or 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
? PSI_L Support with Phase Shedding for Improved
Efficiency at Light Load
? Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
? Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
? Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
? Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
? Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
? Variable Gate Drive Bias: 5V to 12V
? Overcurrent Protection
? Multi-tiered Overvoltage Protection
? Selectable Switching Frequency up to 1MHz
? Simultaneous Digital Soft-Start of Both Outputs
? Processor NorthBridge Voltage Via Single Phase
Power Conversion
? Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over Temperature
PART NUMBER
(Note)
PART
MARKING
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
? Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
ISL6323BCRZ*
ISL6323BIRZ*
ISL6323B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6323B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
- Conforms to AMD SVI Specifications
? Overcurrent Protection
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
? Continuous DCR Current Sensing
? Variable Gate Drive Bias: 5V to 12V
? Simultaneous Digital Soft-Start of Both Outputs
? Selectable Switching Frequency up to 1MHz
? Pb-Free (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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