参数资料
型号: ISL6323BCRZ
厂商: Intersil
文件页数: 20/36页
文件大小: 0K
描述: IC PWM CTRLR SYNC BUCK DL 48QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6323B
down so that a larger positive spike can be sustained without
For Negative Offset (connect R OFS to VCC):
R OFS = --------------------------
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, a
current 8x the average current of all active channels, 8*I AVG ,
flows from FB through a load-line regulation resistor R FB .
The resulting voltage drop across R FB is proportional to the
-
1.6 × R FB
V OFFSET
VDIFF
(EQ. 15)
output current, effectively creating an output voltage droop
with a steady-state value defined as Equation 12:
V DROOP = I AVG ? R FB
(EQ. 12)
V OFS
+
R FB
FB
VREF
E/A
V OUT = V REF – V OFS – ? ------------- ? DCR ? ? ---------- ? --------------- ? ? K ? R FB ?
R SET ?
? 3
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
shown in Equation 13.
? I OUT 400 1 ?
? N ?
(EQ. 13)
I OFS
VCC
In Equation 13, V REF is the reference voltage, V OFS is the
R OFS
-
1.6V
programmed offset voltage, I OUT is the total output current
of the converter, K I is an internal gain determined by the
R SET resistor connected to the RSET pin (K I is defined in
OFS
ISL6323B
+
-
0.3V
+
Equation 10), K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
Output-Voltage Offset Programming
GND
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VCC
The ISL6323B allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the FB pin
and out of the OFS pin. If R OFS is connected to ground, the
voltage across it is regulated to 0.3V, and I OFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I OFS x R FB ). These functions are shown in Figures 9 and 10.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
For Positive Offset (connect R OFS to GND):
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323B through
either the PVI or SVI interface. The ISL6323B manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6323B begins slewing the
DAC at 3.25mV/ μ s until the DAC and target voltage are
equal. Thus, the total time required for a dynamic VID
transition is dependent only on the size of the DAC change.
R OFS = --------------------------
0.3 × R FB
V OFFSET
20
(EQ. 14)
FN6879.1
May 12, 2010
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