参数资料
型号: AT32UC3A1128-AUR
厂商: Atmel
文件页数: 56/97页
文件大小: 0K
描述: MCU AVR32 128K FLASH 100TQFP
产品培训模块: MCU Product Line Introduction
AVR® UC3 Introduction
标准包装: 1
系列: AVR®32 UC3 A1
核心处理器: AVR
芯体尺寸: 32-位
速度: 66MHz
连通性: 以太网,I²C,SPI,SSC,UART/USART,USB OTG
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 69
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 剪切带 (CT)
配用: ATSTK600-RC28-ND - STK600 ROUTING CARD AVR
其它名称: AT32UC3A1128-AURCT
6
AT32UC3A
4.1
Processor and architecture
4.1.1
AVR32 UC CPU
32-bit load/store AVR32A RISC architecture.
– 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading
code density.
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
3 stage pipeline allows one instruction per clock cycle for most instructions.
– Byte, half-word, word and double word memory access.
– Multiple interrupt priority levels.
MPU allows for operating systems with memory protection.
4.1.2
Debug and Test system
IEEE1149.1 compliant JTAG and boundary scan
Direct memory access and programming capabilities through JTAG interface
Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
– Low-cost NanoTrace supported.
Auxiliary port for high-speed trace information
Hardware support for 6 Program and 2 data breakpoints
Unlimited number of software breakpoints supported
Advanced Program, Data, Ownership, and Watchpoint trace supported
4.1.3
Peripheral DMA Controller
Transfers from/to peripheral to/from any memory space without intervention of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Fifteen channels
– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for each ADC
– Two for each TWI Interface
4.1.4
Bus system
High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled
– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet
Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus
B, EBI.
– Round-Robin Arbitration (three modes supported: no default master, last
accessed default
master, fixed default master)
– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master
32058KS–AVR32–01/12
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