参数资料
型号: AT32UC3C1256C-AUR
厂商: Atmel
文件页数: 12/110页
文件大小: 0K
描述: IC MCU AVR32 256K FLASH 100TQFP
产品培训模块: AVR® UC3 Introduction
标准包装: 1
系列: AVR®32 UC3 C
核心处理器: AVR
芯体尺寸: 32-位
速度: 66MHz
连通性: CAN,以太网,I²C,IrDA,LIN,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,I²S,POR,PWM,WDT
输入/输出数: 81
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 16x12b,D/A 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 标准包装
其它名称: AT32UC3C1256C-AURDKR
2011 Microchip Technology Inc.
DS70150E-page 109
dsPIC30F6010A/6015
16.2
Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SSx pin to
perform the Frame Synchronization pulse (FSYNC)
function. The control bit SPIFSD determines whether
the SSx pin is an input or an output (i.e., whether the
module receives or generates the Frame Synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When Frame Synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
16.3
Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb,
even if SSx had been de-asserted in the middle of a
transmit/receive.
16.4
SPI Operation During CPU Sleep
Mode
During Sleep mode, the SPI module is shut down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5
SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
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