参数资料
型号: AT32UC3C2512C-A2UR
厂商: Atmel
文件页数: 79/110页
文件大小: 0K
描述: IC MCU AVR32 512K FLASH 64TQFP
产品培训模块: AVR® UC3 Introduction
标准包装: 1
系列: AVR®32 UC3 C
核心处理器: AVR
芯体尺寸: 32-位
速度: 66MHz
连通性: CAN,以太网,I²C,IrDA,LIN,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,I²S,POR,PWM,WDT
输入/输出数: 45
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 11x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 标准包装
其它名称: AT32UC3C2512C-A2URDKR
70
32117DS–AVR-01/12
AT32UC3C
7.9
Timing Characteristics
7.9.1
Startup, Reset, and Wake-up Timing
The startup, reset, and wake-up timings are calculated using the following formula:
Where
and
are found in Table 7-44.
is the delay relative to RCSYS,
is the period of the CPU clock. If another clock source than RCSYS is selected as CPU
clock the startup time of the oscillator,
, must be added to the wake-up time in the
stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the
”Oscillator Characteristics” on page 57 for more details about oscillator startup times.
ttCONST NCPU tCPU
×
+
=
tCONST
NCPU
tCONST
tCPU
tOSCSTART
Table 7-44.
Maximum Reset and Wake-up Timing
Parameter
Measuring
Max
(in s)
Max
Startup time from power-up, using
regulator
VDDIN_5 rising (10 mV/ms)
Time from V
VDDIN_5=0 to the first instruction entering
the decode stage of CPU. VDDCORE is supplied by
the internal regulator.
2600
0
Startup time from reset release
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
1240
0
Wake-up
Idle
From wake-up event to the first instruction entering
the decode stage of the CPU.
019
Frozen
268
209
Standby
268
209
Stop
268+
212
Deepstop
268+
212
Static
268+
212
tCONST
NCPU
tOSCSTART
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