参数资料
型号: AT32UC3L032-D3HR
厂商: Atmel
文件页数: 12/174页
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
产品培训模块: AVR® UC3 Introduction
标准包装: 1
系列: AVR®32 UC3 L
核心处理器: AVR
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
数据转换器: A/D 9x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-UFLGA
包装: 标准包装
其它名称: AT32UC3L032-D3HRDKR
109
32099I–01/2012
AT32UC3L016/32/64
Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by
writing to the Unlock Register while one or more error bits in SR were set (see Section 9.5.6).
The unlock operation was aborted.
Unlock Register Key Error (URKEY) is set if the Unlock Register was attempted written with
an invalid key.
Unlock Register Read (URREAD) is set if the Unlock Register was attempted read.
Channel Access Unsuccessful (CAU) is set if the channel access was unsuccessful.
Channel Access Successful (CAS) is set if the channel access was successful.
Channel Unlock Expired (EXP) is set if the channel lock expired, with no channel being
accessed after the channel was unlocked.
9.5.6
Error bits
If error bits are set when attempting to unlock a channel, SR.URES will be set. The following SR
bits are considered error bits:
EXP
CAU
URREAD
URKEY
URES
MBERROR
RTRADR
9.5.7
Bus Error Responses
By writing a one to the Bus Error Response Enable bit (CR.BERREN), serious access errors will
be configured to return a bus error to the CPU. This will cause the CPU to execute its Bus Error
Data Fetch exception routine.
The conditions that can generate a bus error response are:
Reading the Unlock Register
Trying to access a locked channel
The SAU HSB master receiving a bus error response from its addressed slave
9.5.8
Disabling the SAU
To disable the SAU, the user must first ensure that no SAU bus operations are pending. This
can be done by checking that the SR.IDLE bit is set.
The SAU may then be disabled by writing a one to the Disable (DIS) bit in CR.
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