参数资料
型号: AT34C02CN-SH-T
厂商: Atmel
文件页数: 3/21页
文件大小: 0K
描述: IC EEPROM 2KBIT 400KHZ 8SOIC
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 1.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: AT34C02CN-SH-TDKR
Atmel AT34C02C
2.
Pin description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-
ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to Vcc) for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as
eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are
left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k ? or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is
connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k ? or less.
Table 2-1.
Atmel AT34C02C write protection modes
Permanent write protect
Reversible write protect
WP pin status
V CC
GND or floating
GND or floating
GND or floating
Pin capacitance (1)
Table 2-2.
register
Not programmed
Programmed
register
Not programmed
Programmed
Part of the array write protected
Full array (2K)
Normal read/write
First-half of array
(1K: 00H - 7FH)
First-half of array
(1K: 00H - 7FH)
Applicable over recommended operating range from T A = 25 C, f = 100 kHz, V CC = +1.7V
Symbol
C I/O
C IN
Test condition
Input/output capacitance (SDA)
Input capacitance (A 0 , A 1 , A 2 , SCL)
Max
8
6
Units
pF
pF
Conditions
V I/O = 0V
V IN = 0V
Note:
1. This parameter is characterized and is not 100% tested
3
5185E–SEEPR–3/11
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