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| 型号： | AT45DB021B-CC |
| 厂商： | Atmel |
| 文件页数： | 4/32页 |
| 文件大小： | 0K |
| 描述： | IC FLASH 2MBIT 20MHZ 9CBGA |
| 标准包装： | 490 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | DataFLASH |
| 存储容量： | 2M（1024 页 x 264 字节） |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 9-TBGA |
| 供应商设备封装： | 9-CBGA（5x5） |
| 包装： | 托盘 |
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5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 4 (pages 9 and 11 ). A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the
desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin
controls the loading of the opcode and the desired buffer or main memory address location
through the SI (serial input) pin. All instructions, addresses, and data are transferred with the
most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA9 - PA0 and BA8 - BA0 where PA9 - PA0
denotes the 10 address bits required to designate a page address and BA8-BA0 denotes the
nine address bits required to designate a byte address within the page.
5.1
5.1.1
4
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers. The DataFlash supports two categories of read modes in relation to
the SCK signal. The differences between the modes are in respect to the inactive state of the
SCK signal as well as which clock cycle data will begin to be output. The two categories, which
are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock
Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 5-3 on page 9
for a complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing ” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
Continuous Array Read
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be
clocked into the device followed by 24 address bits and 32 don’t care bits. The first five bits of
the 24-bit address sequence are reserved for upward and downward compatibility to larger and
smaller density devices (see Notes under “Command Sequence for Read/Write Operations” dia-
gram). The next 10 address bits (PA9- PA0) specify which page of the main memory array to
read, and the last nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte
address within the page. The 32 don’t care bits that follow the 24 address bits are needed to ini-
tialize the read operation. Following the 32 don’t care bits, additional clock pulses on the SCK
pin will result in serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a Con-
tinuous Array Read, the device will continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the crossover from the end of one page to
the beginning of the next page). When the last bit in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
AT45DB021B
1937J–DFLSH–9/05
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相关代理商/技术参数 |
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|---|---|
| AT45DB021B-CI | 功能描述:闪存 DATAFLASH 2M SERIAL 2.7V CBGA IND TEMP RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT45DB021B-CU | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:2-megabit 2.7-volt Only DataFlash |
| AT45DB021B-RC | 功能描述:闪存 2M 2.7V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT45DB021B-RI | 功能描述:闪存 2M 2.7V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT45DB021B-RU | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:2-megabit 2.7-volt Only DataFlash |
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