参数资料
型号: AT45DB041B-CC
厂商: Atmel
文件页数: 15/35页
文件大小: 0K
描述: IC FLASH 4MBIT 20MHZ 14CBGA
标准包装: 325
格式 - 存储器: 闪存
存储器类型: DataFLASH
存储容量: 4M(2048 页 x 264 字节)
速度: 20MHz
接口: SPI 3 线串行
电源电压: 2.7 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 14-LFCBGA
供应商设备封装: 14-CBGA(4.5x7)
包装: 托盘
AT45DB041B
11. AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
11.1
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
CS
t CS
t CSS
t WH
t WL
t CSH
SCK
t V
t HO
t DIS
SO
HIGH IMPEDANCE
VALID OUT
HIGH IMPEDANCE
SI
t SU
VALID IN
tH
11.2
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
CS
t CS
t CSS
t WL
t WH
t CSH
SCK
t V
t HO
t DIS
SO
HIGH Z
VALID OUT
HIGH IMPEDANCE
SI
t SU
VALID IN
t H
11.3
Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
SI
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
15
3443D–DFLSH–2/08
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