参数资料
型号: AT45DB041D-SU
厂商: ATMEL CORP
元件分类: DRAM
英文描述: 4-megabit 2.5-volt or 2.7-volt DataFlash
中文描述: 4M X 1 FLASH 2.7V PROM, PDSO8
封装: 0.208 INCH, GREEN, PLASTIC, EIAJ, SOIC-8
文件页数: 4/53页
文件大小: 1085K
代理商: AT45DB041D-SU
4
3595H–DFLASH–03/07
AT45DB041D
4.
Memory Array
To provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1.
Memory Architecture Diagram
5.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in
Tables 15-1 through
15-7
. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer
or main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most significant
bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the
datasheet using the terminology BEA8 - BFA0 to denote the 9 address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to desig-
nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte
address within the page.
For the “Power of 2” binary page size (256 bytes), the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to desig-
nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte
address within a page.
S
ECTOR 0a =
8
Pa
g
e
s
2,04
8
/2,112 byte
s
S
ECTOR 0b = 24
8
Pa
g
e
s
6
3
,4
88
/65,472 byte
s
Block = 2,04
8
/2,112 byte
s
8
Pa
g
e
s
S
ECTOR 0a
S
E
Pa
g
e = 256/264 byte
s
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE
8
PAGE 9
PAGE 2,046
PAGE 2,047
B
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 1
8
B
S
ECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK
3
0
BLOCK
3
1
BLOCK
3
2
BLOCK
33
BLOCK 254
BLOCK 255
BLOCK 62
BLOCK 6
3
BLOCK 64
BLOCK 65
S
E
S
ECTOR 7 = 256 Pa
g
e
s
65,5
3
6/67,5
8
4 byte
s
BLOCK 2
S
ECTOR 1 = 256 Pa
g
e
s
65,5
3
6/67,5
8
4 byte
s
S
ECTOR 6 = 256 Pa
g
e
s
65,5
3
6/67,5
8
4 byte
s
S
ECTOR 2 = 256 Pa
g
e
s
65,5
3
6/67,5
8
4
byte
s
相关PDF资料
PDF描述
AT45DB041D-SU-2.5 4-megabit 2.5-volt or 2.7-volt DataFlash
AT45DB080 KJL SERIES I
AT45DB080-RC 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash
AT45DB080-RI 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash
AT45DB080-TC 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash
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