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参数资料
| 型号： | AT45DB080-TC |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash |
| 中文描述： | 8M X 1 FLASH 2.7V PROM, 180 ns, PDSO32 |
| 封装： | PLASTIC, MO-142BD, TSOP-32 |
| 文件页数： | 3/18页 |
| 文件大小： | 158K |
| 代理商： | AT45DB080-TC |
AT45DB080
3
buffer 2. To perform a buffer read, the 1-byte opcode must
be followed by the three address bytes comprised of 15
don’t care bits and nine address bits. Following the three
address bytes, an additional don’t care byte must be
clocked in to initialize the read operation. Since the buffer
size is 264-bytes, nine address bits (BFA8-BFA0) are
required to specify the first byte of data to be read from the
buffer. The CS pin must remain low during the loading of
the opcode, the address bytes, the don’t care bytes, and
the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of
the buffer. A low to high transition on the CS pin will termi-
nate the read operation and tri-state the output pins.
MAIN MEMORY PAGE TO BUFFER TRANSFER:
A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. A 1-byte opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the three address bytes
comprised of the three reserved bits, 12 address bits
(PA11-PA0) which specify the page in main memory that is
to be transferred, and nine don’t care bits. The CS pin must
be low while toggling the CLK pin to load the opcode and
the address bytes from the input pins. The transfer of the
page of data from the main memory to the buffer will begin
when the CS pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (t
XFR
), the status register
can be read to determine whether the transfer has been
completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE:
A page of
data in main memory can be compared to the data in buffer
1 or buffer 2. A 1-byte opcode, 60H for buffer 1 and 61H for
buffer 2, is followed by three address bytes consisting of
three reserved bits, 12 address bits (PA11-PA0) which
specify the page in the main memory that is to be com-
pared to the buffer, and nine don't care bits. The loading of
the opcode and the address bits is the same as described
previously. The CS pin must be low while toggling the CLK
pin to load the opcode and the address bytes from the input
pins. On the low to high transition of the CS pin, the 264
bytes in the selected main memory page will be compared
with the 264 bytes in buffer 1 or buffer 2. During this time
(t
XFR
), the status register will indicate that the part is busy.
On completion of the compare operation, bit 6 of the status
register is updated with the result of the compare.
Program
BUFFER WRITE:
Data can be clocked in from the input
pins into either buffer 1 or buffer 2. To load data into either
buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer
2, is followed by the three address bytes comprised of 15
don't care bits and nine address bits (BFA8-BFA0). The
nine address bits specify the first byte in the buffer to be
written. The data is entered following the address bits. If
the end of the data buffer is reached, the device will wrap
around back to the beginning of the buffer. Data will con-
tinue to be loaded into the buffer until a low to high transi-
tion is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE:
Data written into either buffer 1 or buffer
2 can be programmed into the main memory. A 1-byte
opcode, 83H for buffer 1 or 86H for buffer 2, is followed by
the three address bytes consisting of three reserved bits,
12 address bits (PA11-PA0) that specify the page in the
main memory to be written, and nine additional don't care
bits. When a low-to-high transition occurs on the CS pin,
the part will first erase the selected page in main memory to
all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and
should take place in a maximum time of t
EP
. During this
time, the status register will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE:
A previously erased page within
main memory can be programmed with the contents of
either buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1
or 89H for buffer 2, is followed by three address bytes con-
sisting of three reserved bits, 12 address bits (PA11-PA0)
that specify the page in the main memory to be written, and
nine additional don’t care bits. When a low to high transition
occurs on the CS pin, the part will program the data stored
in the buffer into the specified page in the main memory. It
is necessary that the page in main memory that is being
programmed has been previously programmed to all 1s
(erased state). The programming of the page is internally
self timed and should take place in a maximum time of t
P
.
During this time, the status register will indicate that the
part is busy.
MAIN MEMORY PAGE PROGRAM:
This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
clocked into buffer 1 or buffer 2 from the input pins and
then programmed into a specified page in the main mem-
ory. A 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, is
followed by three address bytes comprised of three
reserved bits and 21 address bits. The 12 most significant
address bits (PA11-PA0) select the page in the main mem-
ory where data is to be written, and the next nine address
bits (BFA8-BFA0) select the first byte in the buffer to be
written. After all address bytes are clocked in, the part will
take data from the input pins and store it in one of the data
buffers. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When
there is a low to high transition on the CS pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the program-
ming of the page are internally self timed and should take
place in a maximum of time t
EP
. During this time, the status
register will indicate that the part is busy.
相关PDF资料 |
PDF描述 |
|---|---|
| AT45DB080-TI | 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash |
| AT45DB081B-CNU | 8-megabit 2.5-volt Only or 2.7-volt Only DataFlash |
| AT45DB081B-CU | 8-megabit 2.5-volt Only or 2.7-volt Only DataFlash |
| AT45DB081B-RU | 8-megabit 2.5-volt Only or 2.7-volt Only DataFlash |
| AT45DB081B-TU | 8-megabit 2.5-volt Only or 2.7-volt Only DataFlash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT45DB080-TI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash |
| AT45DB081 | 制造商:Adesto Technologies Corporation 功能描述:ROOT PART: DATAFLASH - Bulk |
| AT45DB081A | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.7-volt Only Serial DataFlash |
| AT45DB081A-CC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SPI Serial EEPROM |
| AT45DB081A-CI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-megabit 2.7-volt Only Serial DataFlash |
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