参数资料
型号: AT45DB080-TI
厂商: ATMEL CORP
元件分类: DRAM
英文描述: 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash
中文描述: 8M X 1 FLASH 2.7V PROM, 180 ns, PDSO32
封装: PLASTIC, MO-142BD, TSOP-32
文件页数: 2/18页
文件大小: 158K
代理商: AT45DB080-TI
AT45DB080
2
the DataFlash uses a parallel interface to sequentially
access its data. The simple sequential access facilitates
hardware layout, increases system reliability, minimizes
switching noise, and reduces package size and active pin
count. The device is optimized for use in many commercial
and industrial applications where high density, low pin
count, low voltage, and low power are essential. Typical
applications for the DataFlash are digital voice storage,
image storage, and data storage. The device operates at
clock frequencies up to 2 MHz with a typical active read
current consumption of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB080 does not require high input voltages for pro-
gramming. The device operates from a single power sup-
ply, 2.7V to 3.6V, for both the program and read
operations. The AT45DB080 is enabled through the chip
select pin (CS) and accessed via an interface consisting of
the parallel input/output (I/O7-I/O0) pins and the clock
(CLK) pin.
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 1-byte opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the CLK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the input pins (I/O7-I/O0).
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ:
A main memory read allows
the user to read data directly from any one of the 4096
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 1-byte opcode, 52H, is followed by 3
address bytes (which comprise the 24 page and byte
address bits) and 60 don’t care bytes. In the AT45DB080,
the first three address bits are reserved for larger density
devices (see Notes on page 8), the next 12 address bits
(PA11-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 60 don’t care bytes which follow the 3
address bytes are sent to initialize the read operation. Fol-
lowing the 60 don’t care bytes, additional pulses on CLK
result in data being output on the output pins (I/O7-I/O0).
The CS pin must remain low during the loading of the
opcode, the address bytes, the don’t care bytes, and the
reading of data. When the end of a page in main memory is
reached during a main memory page read, the device will
continue reading at the beginning of the same page. A low
to high transition on the CS pin will terminate the read oper-
ation and tri-state the output pins.
BUFFER READ:
Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)
BUFFER 1 (264 BYTES)
I/O INTERFACE
CLK
CS
RESET
V
CC
GND
RDY/BUSY
WP
I/O7-I/O0
相关PDF资料
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AT45DB081B-CNU 8-megabit 2.5-volt Only or 2.7-volt Only DataFlash
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AT45DB081A-JC 制造商:未知厂家 制造商全称:未知厂家 功能描述:SPI Serial EEPROM