参数资料
型号: AT49BV1024A
厂商: Atmel Corp.
英文描述: 1-megabit (64K x 16) 3-volt Only Flash Memory
中文描述: 1兆位(64K的× 16)3伏,只有闪存
文件页数: 2/14页
文件大小: 308K
代理商: AT49BV1024A
2
AT49BV/LV1024A
3332B–FLASH–12/03
Block Diagram
Device Operation
READ:
The AT49BV/LV1024A is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE:
When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.
MAIN MEMORY ERASE:
As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main
memory erase operation is internally controlled; it will automatically time to completion.
WORD PROGRAMMING:
Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is
accomplished via the internal device command register and is a four-bus cycle opera-
tion (please refer to the Command Definitions table). The device will automatically
generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified t
BP
cycle time. The Data Polling feature
may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (8K WORDS)
MAIN MEMORY
(56K WORDS)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
2000H
1FFFH
0000H
FFFFH
相关PDF资料
PDF描述
AT49LV1024A 1-megabit (64K x 16) 3-volt Only Flash Memory
AT49LV1024A-45VC 1-megabit (64K x 16) 3-volt Only Flash Memory
AT49LV1024A-45VL 1-megabit (64K x 16) 3-volt Only Flash Memory
AT49BV1604T-90TC 16-Megabit 1M x 16/2M x 8 3-volt Only Flash Memory
AT49BV1604T-90TI 16-Megabit 1M x 16/2M x 8 3-volt Only Flash Memory
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