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参数资料
| 型号： | AT49LV080 |
| 厂商： | Atmel Corp. |
| 英文描述： | 8-Megabit Single 2.7-volt Battery-Voltage Flash Memory(8M位单电源2.7V Battery-Voltage技术闪速存储器) |
| 中文描述： | 8兆位单2.7伏电池电压快闪记忆体（800万位单电源为2.7V电池电压技术闪速存储器） |
| 文件页数： | 2/16页 |
| 文件大小： | 173K |
| 代理商： | AT49LV080 |
AT49BV/LV080(T)
2
The device contains a user-enabled “boot block” protection
feature. Two versions of the feature are available: the
AT49BV/LV080 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BVLV080T locates it at
highest order addresses (“top boot”).
To allow for simple in-system reprogrammability, the
AT49BV/LV080(T) does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by eras-
ing the entire 8 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming time
is a fast 30
μ
s. The end of a program cycle can be option-
ally detected by the DATA polling feature. Once the end of
a byte program cycle has been detected, a new access for
a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
Device Operation
READ:
The AT49BV/LV080(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
ERASURE:
Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
ADDRESS
INPUTS
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
04000H
03FFFH
00000H
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
FC000H
FBFFFH
00000H
AT49BV/LV080T
AT49BV/LV080
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
FFFFFH
FFFFFH
OE
WE
CE
VCC
GND
相关PDF资料 |
PDF描述 |
|---|---|
| AT49LV080T | 8-Megabit Single 2.7-volt Battery-Voltage Flash Memory(8M位单电源2.7V Battery-Voltage技术闪速存储器) |
| AT49BV1024A | 1-megabit (64K x 16) 3-volt Only Flash Memory |
| AT49LV1024A | 1-megabit (64K x 16) 3-volt Only Flash Memory |
| AT49LV1024A-45VC | 1-megabit (64K x 16) 3-volt Only Flash Memory |
| AT49LV1024A-45VL | 1-megabit (64K x 16) 3-volt Only Flash Memory |
相关代理商/技术参数 |
参数描述 |
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| AT49LV102470VC | 制造商:ATMEL 功能描述:IC FLASH MEMORY 1M 3V 40-VSOP |
| AT49LV1024-70VC | 功能描述:IC FLASH 1MBIT 70NS 40VSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
| AT49LV1024-90JC | 功能描述:IC FLASH 1MBIT 90NS 44PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
| AT49LV1024-90VC | 功能描述:IC FLASH 1MBIT 90NS 40VSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
| AT49LV1024-90VI | 功能描述:IC FLASH 1MBIT 90NS 40VSOP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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