- 您现在的位置：买卖IC网 > PDF目录381485 > AT49LV1025 (Atmel Corp.) 1-megabit 3-volt Only Flash Memory(1M位 3V闪速存储器) PDF资料下载
参数资料
| 型号： | AT49LV1025 |
| 厂商： | Atmel Corp. |
| 英文描述： | 1-megabit 3-volt Only Flash Memory(1M位 3V闪速存储器) |
| 中文描述： | 1兆位3伏，只有闪存（100万位3V的闪速存储器） |
| 文件页数： | 2/13页 |
| 文件大小： | 253K |
| 代理商： | AT49LV1025 |
AT49LV1024/1025
2
the read and programming operation of the device. Read-
ing data out of the device is similar to reading from an
EPROM. Reprogramming the AT49LV1024/1025 is per-
formed by erasing a block of data (entire chip or main
memory block) and then programming on a word by word
basis. The typical word programming time is a fast 20 μs.
The end of a program cycle can be optionally detected by
the Data Polling feature. Once the end of a byte program
cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.
Block Diagram
Device Operation
READ:
The AT49LV1024/1025 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high-impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
CHIP ERASE:
When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same Chip Erase com-
mand (See Command Definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.
MAIN MEMORY ERASE:
As an alternative to the chip
erase, a main memory block erase can be performed,
which will erase all words not located in the boot block
region to an FFFFH. Data located in the boot region will not
be changed during a main memory block erase. The Main
Memory Erase command is a six-bus cycle operation. The
address (5555H) is latched on the falling edge of the sixth
cycle while the 30H data input is latched on the rising edge
of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see Main Memory Erase
cycle waveforms. The main memory erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logic “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a four-bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The Data Polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (8K WORDS)
MAIN MEMORY
(56K WORDS)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
2000H
1FFFH
0000H
FFFFH
相关PDF资料 |
PDF描述 |
|---|---|
| AT49LV2048A-70RC | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49LV2048A-70TC | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49BV2048A-90TC | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49BV2048A-90TI | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49LV2048A | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT49LV1025-70JC | 功能描述:IC FLASH 1MBIT 70NS 44PLCC 制造商:microchip technology 系列:- 包装:管件 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:1Mb （64K x 16） 写周期时间 - 字，页:50μs 访问时间:70ns 存储器接口:并联 电压 - 电源:3 V ~ 3.6 V 工作温度:0°C ~ 70°C（TC） 安装类型:表面贴装 封装/外壳:44-LCC（J 形引线） 供应商器件封装:44-PLCC（16.59x16.59） 基本零件编号:AT49LV1025 标准包装:27 |
| AT49LV1025-70VC | 功能描述:IC FLASH 1MBIT 70NS 40VSOP 制造商:microchip technology 系列:- 包装:托盘 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:1Mb （64K x 16） 写周期时间 - 字，页:50μs 访问时间:70ns 存储器接口:并联 电压 - 电源:3 V ~ 3.6 V 工作温度:0°C ~ 70°C（TC） 安装类型:表面贴装 封装/外壳:40-TFSOP（0.488"，12.40mm 宽） 供应商器件封装:40-VSOP 基本零件编号:AT49LV1025 标准包装:160 |
| AT49LV1025-90JC | 功能描述:IC FLASH 1MBIT 90NS 44PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
| AT49LV1025-90VC | 功能描述:IC FLASH 1MBIT 90NS 40VSOP 制造商:microchip technology 系列:- 包装:托盘 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:1Mb （64K x 16） 写周期时间 - 字，页:50μs 访问时间:90ns 存储器接口:并联 电压 - 电源:3 V ~ 3.6 V 工作温度:0°C ~ 70°C（TC） 安装类型:表面贴装 封装/外壳:40-TFSOP（0.488"，12.40mm 宽） 供应商器件封装:40-VSOP 基本零件编号:AT49LV1025 标准包装:160 |
| AT49LV1614-90TC | 功能描述:闪存 16M bit RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。