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参数资料
| 型号： | AT49LV2048A-70RC |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| 中文描述： | 128K X 16 FLASH 3V PROM, 70 ns, PDSO44 |
| 封装： | 0.525 INCH, PLASTIC, SOIC-44 |
| 文件页数： | 3/17页 |
| 文件大小： | 263K |
| 代理商： | AT49LV2048A-70RC |
3
AT49BV/LV2048A
1914D–FLASH–03/02
AT49BV/LV2048
A Block
Diagram
Device
Operation
READ:
The AT49BV/LV2048A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is asserted
on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES:
When the device is first powered on it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET:
A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs. By applying a 12V <Symbol
10pt>± 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if
the boot block program lockout feature has been enabled (see “Boot Block Programming
Lockout Override” section).
ERASURE:
Before a byte or word can be reprogrammed, it must be erased. The erased state
of memory bits is a logic “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase commands.
CHIP ERASE:
The entire device can be erased at one time by using the 6-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t
EC
.
If the boot block lockout has been enabled, the chip erase will not erase the data in the boot
block; it will erase the main memory block and the parameter blocks only. After the chip erase,
the device will return to the read or standby mode.
VCC
GND
OE
WE
CE
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
I/O0 - I/O15
RESET
ADDRESS
INPUTS
Y DECODER
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
Y-GATING
1FFFF
MAIN MEMORY
(112K WORDS)
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
BOOT BLOCK
8K WORDS
04000
03FFF
03000
02FFF
X DECODER
02000
01FFF
00000
相关PDF资料 |
PDF描述 |
|---|---|
| AT49LV2048A-70TC | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49BV2048A-90TC | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49BV2048A-90TI | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49LV2048A | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
| AT49BV2048A | 2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory |
相关代理商/技术参数 |
参数描述 |
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