参数资料
型号: AT49LW040-33JC
厂商: ATMEL CORP
元件分类: DRAM
英文描述: 8-megabit and 4-megabit Firmware Hub Flash Memory
中文描述: 512K X 8 FLASH 3V PROM, 11 ns, PQCC32
封装: PLASTIC, MS-016AE, LCC-32
文件页数: 21/34页
文件大小: 465K
代理商: AT49LW040-33JC
21
AT49LW080/040
1966C
FLASH
03/02
A/A Mux Interface
The following information applies
only
to the AT49LW040/080 when in A/A Mux Mode.
Information on FWH Mode (the standard operating mode) is detailed earlier in this docu-
ment. Electrical characteristics in A/A Mux Mode are provided on pages starting from
page 27.
The AT49LW040/080 is designed to offer a parallel programming mode for faster factory
programming. This mode, called A/A Mux Mode, is selected by having this IC pin high.
The IC pin is pulled down internally in the AT49LW040/080, so a modest current should
be expected to be drawn (see Table 1 on page 3 for further information). Four control
pins dictate data flow in and out of the component: R/C, OE, WE, and RST. R/C is the
A/A Mux control pin used to latch row and column addresses. OE is the data output con-
trol pin (I/O0 - I/O7), drives the selected memory data onto the I/O bus, when active WE
and RST must be at V
IH
.
BUS OPERATION:
All A/A Mux bus cycles can be conformed to operate on most auto-
mated test equipment and PROM programmers.
Notes:
1. When V
PP
V
PPLK
, the memory contents can be read, but not altered.
2. X can be V
IL
or V
IH
for control and address input pins and V
PPLK
or V
PPH1/2
for the VPP
supply pin. See the
DC Characteristics
for V
PPLK
and V
PPH1/2
voltages.
3. See Table 12 on page 18 for Product ID Entry data and addresses.
4. Command writes involving sector erase or program are reliably executed when V
PP
=
V
PPH1/2
and V
CC
= V
CC
± 0.3V.
5. Refer to
A/A Mux Read-only Operations
for valid D
IN
during a write operation.
6. V
IH
and V
IL
refer to the DC characteristics associated with Flash memory output buff-
ers: V
IL
min = 0.5V, V
IL
max = 0.8V, V
IH
min = 2.0V, V
IH
max = V
CC
+ 0.5V.
OUTPUT DISABLE/ENABLE:
With OE at a logic-high level (V
IH
), the device outputs are
disabled. Output pins I/O0 - I/O7 are placed in the high-impedance state. With OE at a
logic-low level (V
IL
), the device outputs are enabled. Output pins I/O0 - I/O7 are placed
in a output-drive state.
ROW/COLUMN ADDRESSES:
R/C is the A/A Mux control pin used to latch row (A0 -
A10) and column addresses (A11 - A18) [AT49LW040], or (A11 - A19) [AT49LW080].
R/C latches row addresses on the falling edge and column addresses on the rising
edge.
RDY/BUSY:
An open drain Ready/Busy output pin provides a hardware method of
detecting the end of a program or erase operation. RDY/Busy is actively pulled low dur-
ing the internal program and erase cycles and is released at the completion of the cycle.
Bus Operations
Mode
RST
OE
WE
Address
V
PP
I/O0 - I/O7
Read
(1)(2)(6)
V
IH
V
IL
V
IH
X
X
D
OUT
Output Disable
(6)
V
IH
V
IH
V
IH
X
X
High-Z
Product ID Entry
(6)
V
IH
V
IL
V
IH
(3)
X
Note 3
Write
(4)(5)(6)
V
IH
V
IH
V
IL
X
X
D
IN
相关PDF资料
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