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参数资料
| 型号： | AT49LW080 |
| 厂商： | Atmel Corp. |
| 英文描述： | 8-megabit and 4-megabit Firmware Hub Flash Memory |
| 中文描述： | 8兆位和4兆位闪存固件集线器 |
| 文件页数： | 9/34页 |
| 文件大小： | 465K |
| 代理商： | AT49LW080 |
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9
AT49LW080/040
1966C
–
FLASH
–
03/02
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
Table 5.
FWH Read Cycle
Clock Cycle
Field Name
FieldContents
(1)
FWH[3:0]
FWH[3:0]
Direction
Comments
1
START
1101b
IN
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field contents
indicate an FWH memory read cycle.
2
IDSEL
0000b
to
1111b
IN
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0],
then that particular device will respond to subsequent
commands.
3 - 9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most significant nibble first.
10
MSIZE
0000b (1 byte)
IN
The FWH will only support single-byte transfers.
11
TAR0
1111b
IN
then float
In this clock cycle, the master (ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus
“
turnaround
cycle
”
.
12
TAR1
1111b (float)
Float then OUT
The FWH takes control of the bus during this cycle.
During the next clock cycle, it will be driving
“
sync
data
”
.
13 - 14
WSYNC
0101b (WAIT)
OUT
The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a.
“
short-sync
”
), for two clock cycles.
This value indicates to the master (ICH) that data is
not yet available from the part. This number of wait-
syncs is a function of the device
’
s access time.
15
RSYNC
0000b (READY)
OUT
During this clock cycle, the FWH will generate a
“
ready-sync
”
(RSYNC) indicating that the least
significant nibble of the least significant byte will be
available during the next clock cycle.
16
DATA
YYYY
OUT
YYYY is the least significant nibble of the least
significant data byte.
17
DATA
YYYY
OUT
YYYY is the most significant nibble of the least
significant data byte.
18
TAR0
1111b
OUT
then float
The FWH Flash memory drives FWH0 - FWH3 to
1111b to indicate a turnaround cycle.
19
TAR1
1111b (float)
Float then
IN
The FWH Flash memory floats its outputs, the master
(ICH) takes control of FWH3 - FWH0.
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相关代理商/技术参数 |
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| AT49LW080-33JC | 功能描述:IC FLASH 8MBIT 33MHZ 32PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
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| AT49LW080-33JX | 功能描述:IC FLASH 8MBIT 33MHZ 32PLCC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:RAM 存储器类型:SDRAM 存储容量:256M（8Mx32） 速度:143MHz 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:托盘 其它名称:Q2841869 |
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