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参数资料
| 型号： | AT6003-4JC |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | Coprocessor Field Programmable Gate Arrays |
| 中文描述： | FPGA, 1600 CLBS, 9000 GATES, PQCC84 |
| 封装： | PLASTIC, MS-018AF, LCC-84 |
| 文件页数： | 10/28页 |
| 文件大小： | 835K |
| 代理商： | AT6003-4JC |
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AT6000(LV) Series
10
memory to configure the FPGA. Addresses change after
the rising edge of the CCLK signal.
CSOUT or I/O
When cascading devices, CSOUT is an output used to
enable other devices. CSOUT should be connected to the
CS input of the downstream device. The CSOUT function is
optional and can be disabled during initial programming
when cascading is not used. When cascading devices,
CSOUT should be dedicated to configuration and not used
as a configurable I/O.
CHECK or I/O
During configuration, CHECK is a TTL input that can be
used to enable the data check function at the beginning of
a configuration cycle. No data is written to the device while
CHECK is low. Instead, the configuration file being applied
to D0 (or D0 - D7, in parallel mode) is compared with the
current contents of the internal configuration RAM. If a mis-
match is detected between the data being loaded and the
data already in the RAM, the ERR pin goes low. The
CHECK function is optional and can be disabled during ini-
tial programming.
ERR or I/O
During configuration, ERR is an output. When the CHECK
function is activated and a mismatch is detected between
the current configuration data stream and the data already
loaded in the configuration RAM, ERR goes low. The ERR
ouput is a registered signal. Once a mismatch is found, the
signal is set and is only reset after the configuration cycle is
restarted. ERR is also asserted for configuration file errors.
The ERR function is optional and can be disabled during
initial programming.
Device Pinout Selection (Max. Number of User I/O)
AT6002
AT6003
AT6005
AT6010
84 PLCC
64 I/O
64 I/O
64 I/O
-
100 VQFP
80 I/O
80 I/O
80 I/O
-
132 PQFP
96 I/O
108 I/O
108 I/O
108 I/O
144 TQFP
95 I/O
120 I/O
108 I/O
120 I/O
208 PQFP
-
-
-
172 I/O
240 PQFP
-
-
-
204 I/O
Bit-stream Sizes
Mode(s)
Type
Beginning Sequence
AT6002
AT6003
AT6005
AT6010
1
Parallel
Preamble
2677
4153
8077
16393
2
Parallel
Preamble
2677
4153
8077
16393
3
Serial
Null Byte/Preamble
2678
4154
8078
16394
4
Serial
Null Byte/Preamble
2678
4154
8078
16394
5
Parallel
Preamble
2677
4153
8077
16393
6
Parallel
Preamble/Preamble
2678
4154
8078
16394
相关PDF资料 |
PDF描述 |
|---|---|
| AT6003-4JI | Coprocessor Field Programmable Gate Arrays |
| AT6003-4QC | Coprocessor Field Programmable Gate Arrays |
| AT6003-4QI | Coprocessor Field Programmable Gate Arrays |
| AT6005-2AC | Coprocessor Field Programmable Gate Arrays |
| AT6005-2AI | Coprocessor Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT6003-4JI | 功能描述:FPGA - 现场可编程门阵列 9K GATE 4NS 84 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| AT6003-4QC | 功能描述:FPGA - 现场可编程门阵列 AT6K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| AT6003-4QI | 功能描述:FPGA - 现场可编程门阵列 AT6K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| AT6003A-2AC | 功能描述:FPGA - 现场可编程门阵列 9000 GATE - 2NS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| AT6003A-2AI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
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