参数资料
型号: AT6005A-4QC
厂商: ATMEL CORP
元件分类: FPGA
英文描述: Coprocessor Field Programmable Gate Arrays
中文描述: FPGA, 3136 CLBS, 15000 GATES, PQFP208
封装: PLASTIC, QFP-208
文件页数: 20/28页
文件大小: 835K
代理商: AT6005A-4QC
AT6000(LV) Series
20
AC Timing Characteristics
3.3V Operation
Notes:
1. TTL buffer delays are measured from a V
IH
of 1.5V at the pad to the internal V
IH
at A. The input buffer load is constant.
2. CMOS buffer delays are measured from a V
IH
of 1/2 V
CC
at the apd to the internal V
IH
at A. The input buffer load is constant.
3. Buffer delay is to a pad voltage of 1.5V with one output switching.
4. Max specifications are the average of mas t
PDLH
and t
PDHL
.
5. Parameter based on characterization and simulation; not tested in production
6. Exact power calculation is available in an Atmel application note.
7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Load of 28 Clock Columns; 5
= Load of 28 Reset Columns; 6 = Tester Load of 50 pF.
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: V
CC
= 3.0V to 3.6V. Temperature = 0
°
C to 70
°
C.
Cell Function
Parameter
From
To
Load
Definition
(7)
-4
Units
Wire
(4)
t
PD
(max)
(4)
A, B, L
A, B
1
1.8
ns
NAND
t
PD
(max)
A, B, L
B
1
3.2
ns
XOR
t
PD
(max)
A, B, L
A
1
4.0
ns
AND
t
PD
(max)
A, B, L
B
1
3.2
ns
MUX
t
PD
(max)
A, B
A
1
4.0
ns
L
A
1
4.9
ns
D-Flip-flop
(5)
t
setup
(min)
A, B, L
CLK
-
3.0
ns
D-Flip-flop
(5)
t
hold
(min)
CLK
A, B, L
-
0
ns
D-Flip-flop
t
PD
(max)
CLK
A
1
3.0
ns
Bus Driver
t
PD
(max)
A
L
2
4.0
ns
Repeater
t
PD
(max)
L, E
E
3
2.3
ns
L, E
L
2
3.0
ns
Column Clock
t
PD
(max)
GCLK, A, ES
CLK
3
3.0
ns
Column Reset
t
PD
(max)
GRES, A, EN
RES
3
3.0
ns
Clock Buffer
(5)
t
PD
(max)
CLOCK PIN
GCLK
4
2.9
ns
Reset Buffer
(5)
t
PD
(max)
RESET PIN
GRES
5
2.8
ns
TTL Input
(1)
t
PD
(max)
I/O
A
3
1.5
ns
CMOS Input
(2)
t
PD
(max)
I/O
A
3
2.3
ns
Fast Output
(3)
t
PD
(max)
A
I/O PIN
6
6.0
ns
Slow Output
(3)
t
PD
(max)
A
I/O PIN
6
12.0
ns
Output Disable
(5)
t
PXZ
(max)
L
I/O PIN
6
5.5
ns
Fast Enable
(3)(5)
t
PXZ
(max)
L
I/O PIN
6
6.5
ns
Slow Enable
(3)(5)
t
PXZ
(max)
L
I/O PIN
6
12.5
ns
Device
Cell Types
Outputs
I
CC
(max)
Cell
(6)
Wire, XWire, Half-adder, Flip-flop
A, B
2.3 μA/MHz
Bus
(6)
Wire, XWire, Half-adder, Flip-flop, Repeater
L
1.3 μA/MHz
Column Clock
(6)
Column Clock Driver
CLK
20 μA/MHz
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