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参数资料
| 型号： | AT6005LV-4AC |
| 厂商： | ATMEL CORP |
| 元件分类： | FPGA |
| 英文描述： | Coprocessor Field Programmable Gate Arrays |
| 中文描述： | FPGA, 3136 CLBS, 15000 GATES, PQFP100 |
| 封装： | 1 MM, PLASTIC, MS-026AED, VQFP-100 |
| 文件页数： | 2/28页 |
| 文件大小： | 835K |
| 代理商： | AT6005LV-4AC |
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AT6000(LV) Series
2
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 to 6400 registers. Pin locations are consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT6000 Series FPGAs utilize a reliable 0.6 μm single-poly,
double-metal CMOS process and are 100% factory-tested.
Atmel's PC- and workstation-based Integrated Develop-
ment System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient commu-
nication over medium and long distances.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells (Figure 1). The array is continuous and
completely uninterrupted from one edge to the other,
except for bus
repeaters
spaced every eight cells
(Figure 2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write access to two North-South and
two East-West buses.
Figure 1.
Symmetrical Array Surrounded by I/O
相关PDF资料 |
PDF描述 |
|---|---|
| AT6005LV-4JC | Coprocessor Field Programmable Gate Arrays |
| AT6005LV-4QC | Coprocessor Field Programmable Gate Arrays |
| AT6010-2JC | Coprocessor Field Programmable Gate Arrays |
| AT6010-2JI | Coprocessor Field Programmable Gate Arrays |
| AT6010-2QC | Coprocessor Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT6005LV-4JC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6005LV-4QC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT-601(40) | 功能描述:衰减器 -互连 RoHS:否 制造商:Pomona Electronics 最大衰减: 容差: 频率范围:DC to 500 MHz 阻抗:50 Ohms 功率额定值:2 W 端接类型:Crimp 连接器类型:BNC Male / Female 工作温度范围:0 C to + 102 C |
| AT60100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | NPN | 8MA I(C) | CHIP |
| AT6010-2JC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
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