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参数资料
| 型号： | AT76C651B |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Digital Reception/ Transmission IC Integrated DVB compliant QAM Demodulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP144 |
| 封装： | LQFP-144 |
| 文件页数： | 5/7页 |
| 文件大小： | 82K |
| 代理商： | AT76C651B |
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AT76C651B
1375BS
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estimation is made over the entire signal sampled by the ADC, thus including the adjacent
channels and the target signal. This ensures that no analog saturation can happen due to the
AGC feedback.
Also, the power estimation of the analog gain control can be used in conjunction with the
AGC2 level (which indicates the power of the QAM signal only) in order to compute the power
of adjacent channels. This may be used to adjust the takeover point (TOP) of external amplifi-
ers when several amplifiers are required on the board (typically in the tuner and after the SAW
filter). Note that an 2WSI-controllable PWM is available for this purpose.
Digital Timing
Recovery
The baseband conversion output is then fed to the timing recovery block. This block integrates
a digital timing loop, which estimates the best resampling time. This information is provided to
a time-continuous filter, which interpolates the baseband signal and produces QAM symbols
at the recovered symbol rate.
The interpolating filter
’
s main property is its continuously autoadaptive bandwidth, which
allows the demodulator to recover a wide range of symbol rate 1/T
S
with the same perfor-
mance and avoids signal aliasing during resampling operation.
Square Root
Raised-cosine
Nyquist Receive
Filter (SRRC)
The SRRC filter, with roll-off factor allowing demodulation of raised-cosine transmitted signals
from 0.11 to 0.4, receives the signal from the timing recovery output and ensures an out-of-
band rejection higher than 43 dB. This significant rejection increases the back-off margin of
the receiver against adjacent channels.
Digital Automatic
Gain Control
(AGC2)
The internal digital AGC performs a fine adjustment of the signal level at the equalizer input.
This AGC only takes into account the QAM signal itself, since adjacent channels have been fil-
tered out by the SRRC, and thus compensates digitally the analog AGC, which may have
reduced the input power due to adjacent channels.
Equalizer
The equalizer is based on algorithms that provide blind and robust acquisition. The equalizer
compensates for the different impairments encountered on the network. Two equalizer struc-
tures can be selected: transversal (powerful for long echoes) or decision feedback (powerful
for strong short echoes).
The equalizer central tap position is configurable. This allows an optimal compensation for
post and pre-cursor echoes. The equalizer comprises 32 taps, which represents a length of
about 6.2 microseconds at 5M bauds. This allows a large compensation for echoes with signif-
icant delays, and a total compensation for significant (small attenuation) short echoes.
Carrier Recovery –
Fine Tuning
The carrier recovery block allows the acquisition and tracking of a frequency offset as high as
12% of the symbol rate, even for low signal-to-noise ratios. The phase comparator algorithm
provides a high-phase noise tolerance, which reduces the tuner cost. The frequency offset
recovered by the chip can be monitored through the 2WSI interface. This information can be
used to readjust the tuner frequency in order to reduce the analog filtering degradation on the
signal and thus improves the bit error rate. This information is also provided automatically to
the DDS in order to recover the frequency with complete accuracy before receive filtering.
Differential
Demodulation for
QPSK
A differential demodulation can be used in a strongly distorted environment in the case of dif-
ferentially encoded QPSK demodulation. This mode provides a stronger robustness against
phase noise but reduces the performance of the receiver by 3 dB, as shown in theory. 2WSI
register QAMSEL must be configured to set this mode.
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