参数资料
型号: AT80C51RD2-RLRUM
厂商: Atmel
文件页数: 17/81页
文件大小: 0K
描述: IC MCU 80C51 HI PERFORM 44VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 标准包装
其它名称: AT80C51RD2-RLRUMDKR
24
4113D–8051–01/09
AT80C51RD2
Table 10-1.
CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (see Figure 10-4 and
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON
SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (see Table 10-2).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
765
4321
0
CIDL
WDTE
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
Description
7CIDL
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6WDTE
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2CPS1
PCA Count Pulse Select
CPS1CPS0
Selected PCA input
0
Internal clock f
CLK PERIPH/6
0
1
Internal clock f
CLK PERIPH/2
1
0 Timer 0 Overflow
1
External clock at ECI/P1.2 pin (max rate = f
CLK PERIPH/4)
1CPS0
0ECF
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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