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参数资料
| 型号： | AT84AD004TD-EB |
| 厂商： | Atmel Corp. |
| 元件分类： | ADC |
| 英文描述： | DUAL 8 BIT 500 MSPS ADC |
| 中文描述： | 双8位500 MSPS的模数转换器 |
| 文件页数： | 46/58页 |
| 文件大小： | 1023K |
| 代理商： | AT84AD004TD-EB |
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46
AT84AD004
5390A–BDC–06/04
ORT
Overvoltage
Recovery Time
The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on
the input is reduced to midscale
PSRR
Power Supply
Rejection Ratio
The ratio of input offset variation to a change in power supply voltage
SFDR
Spurious Free
Dynamic Range
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the highest spectral component (peak spurious spectral component). The peak
spurious component may or may not be a harmonic. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level)
SINAD
Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (-1
dBFS) to the RMS sum of all other spectral components including the harmonics, except DC
SNR
Signal to Noise
Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first 9 harmonics
SSBW
Small Signal Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -10 dB (-10 dBFS)
TA
Aperture delay
The delay between the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] and the time at which VIN and VINB are sampled
TC
Encoding Clock
period
TC1 = minimum clock pulse width (high)
TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
TD1
Time Delay from
Data Transition to
Data Ready
The general expression is TD1 = TC1 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TD2
Time Delay from
Data Ready to
Data
The general expression is TD2 = TC2 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TDO
Digital Data Output
Delay
The delay from the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TDR
Data Ready Output
Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TF
Fall Time
The time delay for the output data signals to fall from 20% to 80% of delta between the low
and high levels
THD
Total Harmonic
Distortion
The ratio expressed in dB of the RMS sum of the first 9 harmonic components to the RMS
input signal amplitude, set at 1 dB below full-scale. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level )
TPD
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the associated
output data made available (not taking into account the TDO)
TR
Rise Time
The time delay for the output data signals to rise from 20% to 80% of delta between the low
and high levels
Table 14.
Definitions of Terms (Continued)
Abbreviation
Definition
Description
相关PDF资料 |
PDF描述 |
|---|---|
| AT84AD004VTD | DUAL 8 BIT 500 MSPS ADC |
| AT84AS003VTP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84XAS003TP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003 | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
| AT84AS003CTP | 10-bit 1.5 Gsps ADC With 1:4 DMUX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT84AD004VTD | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:DUAL 8 BIT 500 MSPS ADC |
| AT84AS001CTPY | 制造商:e2v technologies 功能描述:ADC SGL 500MSPS 12-BIT LVDS 192PIN EBGA - Trays |
| AT84AS001TP-EB | 制造商:e2v technologies 功能描述:EVAL KIT FOR 12-BIT ADC - Bulk |
| AT84AS001VTPY | 制造商:e2v technologies 功能描述:ADC SGL 500MSPS 12-BIT LVDS 192PIN EBGA - Trays |
| AT84AS003 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:10-bit 1.5 Gsps ADC With 1:4 DMUX |
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