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参数资料
| 型号： | AT86RF211 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | FSK Transceiver for ISM Radio Applications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封装： | TQFP-48 |
| 文件页数： | 29/48页 |
| 文件大小： | 582K |
| 代理商： | AT86RF211 |
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29
AT86RF211
1942C
–
WIRE
–
06/02
Control Register (CTRL2)
Table 7.
CTRL2 Overview
Register reset value = (00000057)
16
Table 8.
CTRL2 Detailed Description
Clock Recovery Function
The clock recovery function is activated by setting to
‘
1
’
the DATACLK bit of the CTRL1
register.
The clock recovery function provides on DATACLK pin the data clock, synchronized on
the received data flow. The targeted position for the rising edge of the clock is the mid-
dle of the data bit. It is then easy for the microcontroller to read without synchro troubles.
Clock recovery mechanism is based on the generation of a basic data clock with a
period given by DATARATE of CTRL2 with a step of about 100 ns. This basic clock is
synchronized on the received data flow with a phase correction step fixed by DATATOL
of CTRL2 register (step of about 100 ns also).
So, DATATOL can
–
compensate for the difference between the read data rates from transmitter
and receiver (fixed by DATARATE).
–
allow fast initial synchronization of data clock, avoiding bit transition times
and converge toward the middle of the bit.
–
keep the right data rate (no additional and no removed bit) when a noisy
data with bad bit transition position arrives.
The best value of DATATOL is a trade-off between these considerations. The typical
recommended value of RATETOL is 2% of DATARATE.
Name
DATARATE
DATATOL
LDCK
N0LD1
N1LD2
nbit
31-18
17-10
9
8-5
4-0
init
(0000)
16
(00)
16
0
(0010)
2
(10111)
2
Name
Number of
bits
Comments
DATARATE
14
Received DATAMSG rate
This value must be programmed to have the DATACLK activated.
(selected with DATACLK bit in CTRL1 register).
Value from 1 kbps to 50 kbps
reset value: (0000)
16
DATATOL
8
Tolerance for DATACLK, clock recovery
Recommended value = 2% of the rate.
reset value: (00)
16
LDCK
1
Clock frequency is doubled to increase precision of PLL lock detection
0: 10 MHz clock frequency
1: doubled clock frequency
reset value: 0
N0LD2
4
PLL unlock condition trigger
Recommended values are reset values
reset value: (0010)
2
N1LD2
5
PLL lock condition trigger
Recommended values are reset values
reset value: (10111)
2
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