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参数资料
型号： AT86RF212-ZUR
厂商： Atmel
文件页数： 124/172页
文件大小： 0K
描述： TXRX AVR LOW PWR/VOLTAGE 32PQFN
标准包装： 1
频率： 700MHz，800MHz，900MHz
数据传输率 - 最大： 250kbps
调制或协议： 802.15.4 Zigbee，6LoWPAN，ISM
应用： ISM，ZigBee?
功率 - 输出： 10dBm
灵敏度： -110dBm
电源电压： 1.8 V ~ 3.6 V
电流 - 接收： 9.2mA
电流 - 传输： 25mA
数据接口： PCB，表面贴装
天线连接器： PCB，表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 32-VFQFN 裸露焊盘
包装： 标准包装
其它名称： AT86RF212-ZURDKR
7.8.3 PLL Settling Time and Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON,
the settling time is typically t TR4 = 200 μs (50 μs plus 150 μs settling time of the analog
voltage regulator AVREG), including PLL self calibration. For more information, refer to
Table 5-1 and section 7.8.4. The locking of the PLL is indicated with the interrupt IRQ_0
(PLL_LOCK).
Switching between channels within a frequency band in PLL_ON or RX_ON states is
typically done within t TR20 = 11 μs. This makes the radio transceiver highly suitable for
frequency hopping applications.
The PLL frequency in PLL_ON and receive states is 1 MHz below the PLL frequency in
transmit states. When starting the transmit procedure, the PLL frequency is changed to
the transmit frequency within a period of t TR23 = 16 μs before really starting the
transmission. After the transmission, the PLL settles back to the receive frequency
within a period of t TR24 = 32 μs. These frequency changes do not generate the interrupt
IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK).
7.8.4 Calibration Loops
Due to variation of temperature, supply voltage, and center frequency, the VCO
characteristics may vary.
To ensure a stable operation, two automated control loops are implemented: center
frequency and delay cell calibration. Both calibration loops are initiated automatically
when the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON.
Additionally, both calibration loops are initiated when the PLL changes to a different
frequency setting.
If the PLL operates for a long time on the same channel or the operating temperature
changes significantly, the calibration loops should be initiated manually. The
recommended calibration interval is 5 minutes or less.
Both calibration loops can be initiated manually by SPI command. To start the
calibration, the device should be in state PLL_ON.
The center frequency calibration can be initiated by setting PLL_CF_START = 1
(register 0x1A, PLL_CF). Center frequency calibration generates (if enabled) a
PLL_UNLOCK interrupt. The calibration loop is completed when the PLL_LOCK
interrupt (if enabled) occurs. The duration of the center frequency calibration loop
depends on the difference between the current CF value and the final CF value. During
the calibration, the CF value is incremented or decremented. Each step takes 8 μs. The
minimum time is 8 μs; the maximum time is 270 μs. The recommended procedure to
start the center frequency calibration is to read the register 0x1A (PLL_CF), to set the
PLL_CF_START register bit to 1, and to write the value back to the register.
The delay cell calibration can be initiated by setting the bit PLL_DCU_START of
register 0x1B (PLL_DCU) to 1. The delay time of the programmable delay unit is
adjusted to the correct value. The calibration works as successive approximation and is
independent of the values in the register 0x1B (PLL_DCU). The duration of the
calibration is t TR22 = 10 μs.
During both calibration processes, no correct receive or transmit operation is possible.
The recommended state for the calibration is therefore PLL_ON, but calibration is not
blocked at receive or transmit states.
Both calibrations can be executed concurrently.
124
AT86RF212
8168C-MCU Wireless-02/10
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