参数资料
型号: AT87251G2D-3CSUM
厂商: Atmel
文件页数: 61/77页
文件大小: 0K
描述: IC 8051 MCU 32K OTP 24MHZ 40DIP
标准包装: 216
系列: 8x251
核心处理器: C251
芯体尺寸: 8/16-位
速度: 24MHz
连通性: EBI/EMI,I²C,Microwire,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
64
AT/TSC8x251G2D
4135F–8051–11/06
Notes:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:Port 0 26 mA
Ports 1-3 15 mA
Maximum Total IOL for all: Output Pins 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change
from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
4. Typical values are obtained using VDD = 5 V and TA = 25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3VDD will be recog-
nized as a logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1.
Figure 28.
IDD/IDL Versus Frequency; VDD = 4.5 to 5.5 V
Note:
1. The clock prescaler is not used: FOSC = FXTAL.
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
40
30
20
10
0
IDD/I
D
L(mA
)
Frequency at XTAL(1) (MHz)
2
4
6
8
10
12
14
16
18
20
22
24
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