参数资料
型号: AT87C5112
厂商: Atmel Corp.
英文描述: 8-bit Microcontroller with A/D Converter
中文描述: 8位微控制器与A / D转换器
文件页数: 54/97页
文件大小: 1229K
代理商: AT87C5112
54
AT8xC5112
4191B
8051
04/03
The CMOD SFR
includes three additional bits associated with the PCA (See Figure 23
and Table 41).
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer
(CF) and each module (Refer to Table 42).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
The watchdog timer function is implemented in module 4 (See Figure 26).
2.
f
osc
= oscillator frequency
Table 42.
CCON: PCA Counter Control Register
CCON Address OD8H
7
6
5
4
3
2
1
0
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
Mnemonic
Description
7
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or
software but can only be cleared by software.
6
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be
cleared by software to turn the PCA counter off.
5
-
Not implemented, reserved for future use.
(1)
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
4
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
3
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
2
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
1
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
0
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
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