参数资料
型号: AT87C51RB2-RLTUM
厂商: Atmel
文件页数: 73/84页
文件大小: 0K
描述: IC 8051 MCU 16K OTP 40MHZ 44VQFP
标准包装: 800
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40/20MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
2007-2012 Microchip Technology Inc.
DS70292G-page 77
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.0
RESETS
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDTO: Watchdog Timer Reset
CM: Configuration Mismatch Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 8. “Reset” (DS70192) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
sheet for device-specific register and bit
information.
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
MCLR
VDD
Internal
Regulator
BOR
Sleep or Idle
RESET Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect
POR
Configuration Mismatch
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