参数资料
| 型号： | AT88SA100S-TSU-T |
| 厂商： | Atmel |
| 文件页数： | 11/23页 |
| 文件大小： | 0K |
| 描述： | IC BATT AUTHENTICATION SOT23-3 |
| 产品培训模块： | CryptoAuthentication™ Introduction |
| 标准包装： | 1 |
| 系列： | CryptoAuthentication™ |
| 功能： | 电池验证 |
| 电源电压： | 2.7 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-236-3，SC-59，SOT-23-3 |
| 供应商设备封装： | SOT-3 |
| 包装： | 标准包装 |
| 其它名称： | AT88SA100S-TSU-TDKR |
5.4
5.4.1
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and the AT88SA100S will fall out
of synchronization with each other. In order to speed recovery, the AT88SA100S implements a timeout that forces the
AT88SA100S to sleep. See Section 5.4.1.
IO Timeout
After a leading transition for any data token has been received, the AT88SA100S will expect the remaining bits of the token to
be properly received by the chip within the t TIMEOUT interval. Failure to send enough bits or the transmission of an illegal token
(a low pulse exceeding t ZLO ) will cause the chip to enter the sleep state after the t TIMEOUT interval.
The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the
IO Timeout circuitry is enabled until the last expected data bit is received.
Note:
The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the
t TIMEOUT interval while the time between bits may not
In order to limit the active current if the AT88SA100S is inadvertently awakened, the IO timeout circuitry is also enabled when
the AT88SA100S receives a wake-up. If the first token does not come within the t TIMEOUT interval, then the AT88SA100S will go
back to the sleep mode without performing any operations.
The IO timeout circuitry is disabled when the chip is busy executing a command.
5.4.2
Synchronization Procedures
When the system and the AT88SA100S fall out of synchronization, the system will ultimately end up sending a Transmit flag
which will not generate a response from the AT88SA100S. The system should implement its own timeout which waits for
t TIMEOUT during which time the AT88SA100S should go to sleep automatically. At this point, the system should send a Wake
token and after t WLO + t WHI , a Transmit token. The 0x11 status indicates that the resynchronization was successful.
It may be possible that the system does not get the 0x11 code from the AT88SA100S for one of the following reasons:
1.
2.
3.
The system did not wait a full t TIMEOUT delay with the IO signal idle in which case the AT88SA100S may have
interpreted the Wake token and Transmit flag as a data bits. Recommended resolution is to wait twice the t TIMEOUT
delay and re-issue the Wake token.
The AT88SA100S went into the sleep mode for some reason while the system was transmitting data. In this case,
the AT88SA100S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted
bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal
flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of
a correct CRC. Recommended resolution is to wait the t TIMEOUT delay and re-issue the Wake token.
There is some internal error condition within the AT88SA100S which will be automatically reset after a t WATCHDOG
interval, see below. There is no way to externally reset the AT88SA100S – the system should leave the IO pin idle
for this interval and issue the Wake token.
5.5
Watchdog Failsafe
After the Wake token has been received by the AT88SA100S, a watchdog counter is started within the chip. After t WATCHDOG ,
the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO
transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of the AT88SA100S including any IO synchronization issue, power consumption will fall to the low sleep level
automatically.
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT88SA102S | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:CryptoAuthentication |
| AT88SA102S_10 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Atmel CryptoAuthentication |
| AT88SA102S_11 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Atmel CryptoAuthentication Product Authentication Chip |
| AT88SA102S-SH-T | 功能描述:序列号注册 Product Auth. IC CryptoAuth SHA-256 RoHS:否 制造商:Maxim Integrated 数据总线宽度: 电源电压-最大: 电源电压-最小: 最大工作温度: 最小工作温度: 安装风格: 封装 / 箱体: |
| AT88SA102S-TH-T | 功能描述:序列号注册 58951-Eb CryptoAuth SHA-256 GRN RoHS:否 制造商:Maxim Integrated 数据总线宽度: 电源电压-最大: 电源电压-最小: 最大工作温度: 最小工作温度: 安装风格: 封装 / 箱体: |
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