参数资料
型号: AT89C5131A-RDTUM
厂商: Atmel
文件页数: 47/176页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K USB 64VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 800
系列: AT89C513x
核心处理器: C52X2
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: LED,POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-LQFP
包装: 托盘
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
138
AT89C5131
4136C–USB–04/05
Table 95. UEPCONX Register
UEPCONX (S:D4h)
USB Endpoint X Control Register
Note:
Reset Value = 80h when UEPNUM = 0 (default Control Endpoint)
Reset Value = 00h otherwise for all other endpoints
765
43210
EPEN
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit Number
Bit
Mnemonic
Description
7
EPEN
Endpoint Enable
Set this bit to enable the endpoint according to the device configuration.
Endpoint 0 will always be enabled after a hardware or USB bus reset and
participate in the device configuration.
Clear this bit to disable the endpoint according to the device configuration.
6-
Reserved
The value read from this bit is always 0. Do not set this bit.
5-
Reserved
The value read from this bit is always 0. Do not set this bit.
4-
Reserved
The value read from this bit is always 0. Do not set this bit.
3DTGL
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and
accepted.
This bit is cleared by hardware when a valid DATA1 packet is received and
accepted.
2EPDIR
Endpoint Direction
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous
endpoints.
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous
endpoints.
This bit has no effect for Control endpoints.
1-0
EPTYPE[1:0]
Endpoint Type
Set this field according to the endpoint configuration (Endpoint 0 will always be
configured as control):
00Control endpoint
01Isochronous endpoint
10Bulk endpoint
11Interrupt endpoint
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