参数资料
型号: AT89C51CC01UA-RLTUM
厂商: Atmel
文件页数: 3/123页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44-VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 800
系列: AT89C CAN
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: CAN,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
产品目录页面: 616 (CN2011-ZH PDF)
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
其它名称: AT89C51CC01UARLTUM
PIC18F2XK20/4XK20
DS41303G-page 100
2010 Microchip Technology Inc.
REGISTER 7-1:
EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can be set by software, but not cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1
= Access Flash program memory
0
= Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1
= Access Configuration registers
0
= Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row (Block) Erase Enable bit
1
= Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0
= Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1
= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0
= The write operation completed
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1
= Allows write cycles to Flash program/data EEPROM
0
= Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1
= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0
= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0
= Does not initiate an EEPROM read
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
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