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参数资料
型号： AT89C51IC2-RLRUM
厂商： Atmel
文件页数： 113/140页
文件大小： 0K
描述： IC 8051 MCU 32K FLASH 44-VQFP
产品培训模块： MCU Product Line Introduction
标准包装： 1,500
系列： 89C
核心处理器： 8051
芯体尺寸： 8-位
速度： 40MHz
连通性： I²C，SPI，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 34
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 1.25K x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 44-LQFP
包装： 剪切带 (CT)
其它名称： AT89C51IC2-RLRUMCT
74
AT89C51IC2
4301D–8051–02/08
Figure 28. Full-Duplex Master-Slave Interconnection
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift
register. The Byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received Byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately trans-
ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift reg-
ister) at least one bus cycle before the Master SPI starts a transmission. If the write to
the data register is late, the SPI transmits the data already in the shift register from the
previous transmission. The maximum SCK frequency allowed in slave mode is F
CLK PERIPH
/4.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 29 and Figure 30).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
8-bit Shift register
SPI
Clock Generator
Master MCU
8-bit Shift register
MISO
MOSI
SCK
VSS
VDD
SS
Slave MCU
1.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,
the Master SPI should be configured before the Slave SPI.
2.
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
3.
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
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