参数资料
型号: AT89C51RC2-RLRUL
厂商: Atmel
文件页数: 100/127页
文件大小: 0K
描述: MCU 8051 32K FLASH 3V 44-VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 标准包装
其它名称: AT89C51RC2-RLRULDKR
74
AT89C51RB2/RC2
4180E–8051–10/06
Figure 31. SPI Interrupt Requests Generation
Registers
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON)
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
Table 56 describes this register and explains the use of each bit
Table 56. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter
SPI
CPU Interrupt Request
SPIF
76
54
32
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit Mnemonic
Description
7
SPR2
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
6
SPEN
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
5SSDIS
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
.
4MSTR
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
3CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
2CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
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