参数资料
型号: AT89S4051
厂商: Atmel Corp.
英文描述: 8-bit Microcontroller with 2K/4K Bytes Flash
中文描述: 8位闪存微控制器2K/4K字节
文件页数: 12/45页
文件大小: 981K
代理商: AT89S4051
12
3390C–MICRO–7/05
AT89S2051/S4051
13. Interrupts
The AT89S2051/S4051 provides 6 interrupt sources: two external interrupts, two timer inter-
rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the
system reset each have a separate program vector at the start of the program memory space.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the
interrupt enable register IE. The IE register also contains a global disable bit, EA, which disables
all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the interrupt priority registers IP and IPH. An interrupt service routine in progress
can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower
priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two
requests of different priority levels are pending at the end of an instruction, the request of higher
priority level is serviced. If requests of the same priority level are pending at the end of an
instruction, an internal polling sequence determines which request is serviced. The polling
sequence is based on the vector address; an interrupt with a lower vector address has higher
priority than an interrupt with a higher vector address. Note that the polling sequence is only
used to resolve pending requests of the same priority level.
The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated,
depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-
rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears
the flag that generated an external interrupt only if the interrupt was transition-activated. If the
interrupt was level activated, then the external requesting source (rather than the on-chip hard-
ware) controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI in SCON. Neither of these
flags is cleared by hardware when the service routine is vectored to. In fact, the service routine
normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in
software.
The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware
when the service routine is vectored to and must be cleared by software.
Most of the bits that generate interrupts can be set or cleared by software, with the same result
as though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software.
Interrupt
Source
Vector Address
System Reset
RST or POR or BOD
0000H
External Interrupt 0
IE0
0003H
Timer 0 Overflow
TF0
000BH
External Interrupt 1
IE1
0013H
Timer 1 Overflow
TF1
001BH
Serial Port
RI or TI
0023H
Analog Comparator
CF
0033H
相关PDF资料
PDF描述
AT89S4051-24PC 8-bit Microcontroller with 2K/4K Bytes Flash
AT89S4051-24PI 8-bit Microcontroller with 2K/4K Bytes Flash
AT89S4051-24PU 8-bit Microcontroller with 2K/4K Bytes Flash
AT89S4051-24SC 8-bit Microcontroller with 2K/4K Bytes Flash
AT89S4051-24SI 8-bit Microcontroller with 2K/4K Bytes Flash
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