参数资料
型号: AT89S52-24PC
厂商: Atmel
文件页数: 28/37页
文件大小: 0K
描述: IC MCU 8K FLASH 24MHZ 40-DIP
标准包装: 9
系列: 89S
核心处理器: 8051
芯体尺寸: 8-位
速度: 24MHz
连通性: UART/USART
外围设备: WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
2010 Microchip Technology Inc.
DS41190G-page 35
PIC12F629/675
5.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer
5.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
5.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator rated up to 37 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 9-2 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the system LP oscillator, the user must provide
a software time delay to ensure proper oscillator
start-up.
While enabled, TRISIO4 and TRISIO5 are set. GP4
and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read
‘1’.
5.6
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
Timer1 must be on (T1CON<0>)
TMR1IE bit (PIE1<0>) must be set
PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine on an overflow.
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Note:
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
Note:
The oscillator requires a start-up and stabi-
lization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 000u
0Ch
PIR1
EEIF
ADIF
CMIF
—TMR1IF 00-- 0--0 00-- 0--0
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
8Ch
PIE1
EEIE
ADIE
CMIE
—TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘
0’. Shaded cells are not used by the Timer1 module.
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