参数资料
型号: AT89S8253-24AI
厂商: Atmel
文件页数: 24/60页
文件大小: 0K
描述: IC 8051 MCU FLASH 12K 44TQFP
标准包装: 160
系列: 89S
核心处理器: 8051
芯体尺寸: 8-位
速度: 24MHz
连通性: SPI,UART/USART
外围设备: POR,WDT
输入/输出数: 32
程序存储器容量: 12KB(12K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
30
3286P–MICRO–3/10
AT89S8253
Figure 14-8. SPI Transfer Format with CPHA = 0
Note:
*Not defined but normally MSB of character just received
Figure 14-9. SPI Transfer Format with CPHA = 1
Note:
*Not defined but normally LSB of previously transmitted character
15. Interrupts
The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all
shown in Figure 15-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 15-1 shows that bit position IE.6 is unimplemented. User software should not
write a 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The serial interrupt is the logical OR of bits RI and TI in register SCON and also bit SPIF in
SPSR (if SPIE in SPCR is set). None of these flags is cleared by hardware when the service rou-
tine is vectored to. The service routine may have to determine whether the UART or SPI
generated the interrupt.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
MSB
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
MSB
*
65
4
3
2
1
LSB
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
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