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参数资料
| 型号： | AT90RF135602 |
| 厂商： | Atmel Corp. |
| 英文描述： | INTEGRATED 13.56 MHz CONTACTLESS READER WITH EMBEDED SOFTWARE |
| 中文描述： | 集成了嵌入式软件13.56MHz的非接触式读卡器 |
| 文件页数： | 12/35页 |
| 文件大小： | 806K |
| 代理商： | AT90RF135602 |
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12
4407A–SCR–04/05
The interconnection between Master and Slave CPUs with SPI is shown in Figure 7.
The system consists of two shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
each data packet, the Master will synchronize the Slave by pulling high the Slave Select,
SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line.
This must be handled by user software before communication can start. When this is
done, writing a byte to the SPI Data Register starts the SPI clock generator, and the
hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-
ator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit
(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue
to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high
the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for
later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated
as long as the SS pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in
the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming byte
will be kept in the Buffer Register for later use.
Figure 7.
SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive
direction. This means that bytes to be transmitted cannot be written to the SPI Data
Register before the entire shift cycle is completed. When receiving data, however, a
received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To
ensure correct sampling of the clock signal, the frequency of the SPI clock should never
exceed f
clkio
/4.
SHIFT
ENABLE
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相关代理商/技术参数 |
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|---|---|
| AT90RFD-09 | 功能描述:KIT REF DESIGN FOR AT90RF135602 RoHS:否 类别:RF/IF 和 RFID >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:用于 200/300 系列的欧盟开发套件 适用于相关产品:Zensys RF 模块 所含物品:开发板，模块，编程器，软件，线缆，电源 其它名称:703-1019Q3225667 |
| AT90S1200 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-Bit Microcontroller with 1K bytes In-System Programmable Flash |
| AT90S1200/A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:AT90S1200/A Rev. F Errata [Updated 9/01. 2 Pages] |
| AT90S1200_02 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:8-bit Microcontroller with 1K Byte of In-System Programmable Flash |
| AT90S1200-12PC | 功能描述:8位微控制器 -MCU 1K FLASH 5V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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