参数资料
型号: AT90USB1286-AUR
厂商: Atmel
文件页数: 33/106页
文件大小: 0K
描述: MCU AVR 128K FLASH 16MHZ 64TQFP
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 1,000
系列: AVR® 90USB
核心处理器: AVR
芯体尺寸: 8-位
速度: 16MHz
连通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 48
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
其它名称: AT90USB1286-AUR-ND
AT90USB1286-AURTR
32
7593L–AVR–09/12
AT90USB64/128
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section “I/O-ports” on page 71. The XMEM
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to Fig-
ure 6-6 on page 33 (this figure shows the wave forms without wait-states). When ALE goes from
high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the
XMEM interface is enabled, also an internal access will cause activity on address, data and ALE
ports, but the RD and WR strobes will not toggle during internal access. When the External
Memory Interface is disabled, the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM. Figure 6-5 illustrates how to connect an external SRAM to
the AVR using an octal latch (typically “74 × 573” or equivalent) which is transparent when G is
high.
6.5.3
Address latch requirements
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
D to Q propagation delay (t
PD)
Data setup time before G low (t
SU)
Data (address) hold time after G low (
TH)
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
h = 5ns. Refer to tLAXX_LD/tLLAXX_ST in “External data memory timing” Tables 31-7
through Tables 31-13 on pages 399 - 401. The D-to-Q propagation delay (t
PD) must be taken
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
SU) must not exceed address valid to ALE low (tAVLLC) minus PCB
wiring delay (dependent on the capacitive load).
Figure 6-5.
External SRAM connected to the AVR.
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
DQ
G
AD7:0
ALE
A15:8
RD
WR
AVR
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