参数资料
型号: AT90USB1286-MUR
厂商: Atmel
文件页数: 96/106页
文件大小: 0K
描述: MCU AVR 128K FLASH 16MHZ 64QFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 4,000
系列: AVR® 90USB
核心处理器: AVR
芯体尺寸: 8-位
速度: 16MHz
连通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 48
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: AT90USB1286-MUR-ND
AT90USB1286-MURTR
9
7593L–AVR–09/12
AT90USB64/128
2.2.8
Port E (PE7..PE0)
Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
2.2.9
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10
D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22
Ω resistor.
2.2.11
D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22
Ω resistor.
2.2.12
UGND
USB Pads Ground.
2.2.13
UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.14
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1F).
2.2.15
VBUS
USB VBUS monitor and OTG negociations.
2.2.16
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.17
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
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