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参数资料
| 型号： | AT91M40800-33AU-999 |
| 厂商： | Atmel |
| 文件页数： | 16/18页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT RISC 100LQFP |
| 产品培训模块： | MCU Product Line Introduction |
| 标准包装： | 1,000 |
| 系列： | AT91 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，UART/USART |
| 外围设备： | POR，WDT |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 带卷 (TR) |
7
1348FS–ATARM–13-Apr-06
AT91M40800
7.
Product Overview
7.1
Power Supply
The AT91M40800 microcontroller has a unique type of power supply pin – VDD. The VDD pin
supplies the I/O pads and the device core. The supported voltage range on V
DD is 1.8V to 3.6V.
7.2
Input/Output Considerations
The AT91M40800 microcontroller I/O pads are 5V-tolerant, enabling them to interface with
external 5V devices without any additional components. Thus, the devices accept 5V (3V) on the
inputs even if powered at 3V (2V). For further information, refer to the “AT91M40800 Electrical
Characteristics” datasheet.
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum
flexibility. It is recommended that in any application phase, the inputs to the AT91M40800 micro-
controller be held at valid logic levels to minimize the power consumption.
7.3
Master Clock
The AT91M40800 microcontroller has a fully static design and works on the Master Clock
(MCK), provided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is multi-
plexed with a general-purpose I/O line. While NRST is active, MCKO remains low. After the
reset, the MCKO is valid and outputs an image of the MCK signal. The PIO controller must be
programmed to use this pin as standard I/O line.
7.4
Reset
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.
7.4.1
NRST Pin
NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized
internally to the MCK. The signal presented on MCKI must be active within the specification for a
minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation.
The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
7.4.2
Watchdog Reset
The watchdog can be programmed to generate an internal reset. In this case, the reset has the
same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode
and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the
internal reset, the NRST pin has priority.
7.5
Emulation Functions
7.5.1
Tri-state Mode
The AT91M40800 microcontroller provides a Tri-state mode, which is used for debug purposes.
This enables the connection of an emulator probe to an application board without having to des-
older the device from the target board. In Tri-state mode, all the output pin drivers of the
AT91M40800 microcontroller is disabled.
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