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| 型号： | AT91M42800A-33CJ-999 |
| 厂商： | Atmel |
| 文件页数： | 10/27页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT RISC 144BGA |
| 标准包装： | 1 |
| 系列： | AT91 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，SPI，UART/USART |
| 外围设备： | POR，WDT |
| 输入/输出数： | 54 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 144-LFBGA |
| 包装： | 剪切带 (CT) |
| 其它名称： | AT91M42800A-33CJ-999CT |
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18
1779ES–ATARM–14-Apr-06
AT91M42800A
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard
interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be
asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to
IRQ3.
The 8-level priority encoder allows the customer to define the priority between the different NIRQ
interrupt sources.
Internal sources are programmed to be level sensitive or edge triggered. External sources can
be programmed to be positive or negative edge triggered or high- or low-level sensitive.
8.4.4
PIO: Parallel I/O Controller
The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external
signal of a peripheral to optimize the use of available package pins. These lines are controlled
by two separate and identical PIO Controllers called PIOA and PIOB. Each PIO controller also
provides an internal interrupt signal to the Advanced Interrupt Controller and insertion of a sim-
ple input glitch filter on any of the PIO pins.
8.4.5
SF: Special Function
The AT91M42800A provides registers that implement the following special functions.
Chip Identification
RESET Status
8.5
User Peripherals
8.5.1
USART: Universal Synchronous/Asynchronous Receiver Transmitter
The AT91M42800A provides two identical, full-duplex, universal synchronous/asynchronous
receiver/transmitters that interface to the APB and are connected to the Peripheral Data
Controller.
The main features are:
Programmable Baud Rate Generator with External or Internal Clock, as well as Slow Clock
Parity, Framing and Overrun Error Detection
Line Break Generation and Detection
Automatic Echo, Local Loopback and Remote Loopback channel modes
Multi-drop mode: Address Detection and Generation
Interrupt Generation
Two Dedicated Peripheral Data Controller channels
5-, 6-, 7-, 8- and 9-bit character length
8.5.2
TC: Timer/Counter
The AT91M42800A features two Timer/Counter blocks, each containing three identical 16-bit
Timer/Counter channels. Each channel can be independently programmed to perform a wide
range of functions including frequency measurement, event counting, interval measurement,
pulse generation, delay timing and pulse-width modulation.
Each Timer/Counter (TC) channel has 3 external clock inputs, 5 internal clock inputs, and 2
multi-purpose input/output signals that can be configured by the user. Each channel drives an
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