参数资料
型号: AT91RM9200-CI-002
厂商: Atmel
文件页数: 24/41页
文件大小: 0K
描述: IC ARM9 MCU 256 BGA
标准包装: 126
系列: AT91
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 180MHz
连通性: EBI/EMI,以太网,I²C,MMC,SPI,SSC,UART/USART,USB
外围设备: POR
输入/输出数: 122
程序存储器容量: 128KB(128K x 8)
程序存储器类型: ROM
RAM 容量: 48K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 256-BGA
包装: 托盘
30
1768MS–ATARM–09-Jul-09
AT91RM9200
10 and 100 Mbits per second data throughput capability
Full- and half-duplex operation
MII or RMII interface to the physical layer
Register interface to address, status and control registers
DMA interface, operating as a master on the Memory Controller
Interrupt generation to signal receive and transmit completion
28-byte transmit and 28-byte receive FIFOs
Automatic pad and CRC generation on transmitted frames
Address checking logic to recognize four 48-bit addresses
Supports promiscuous mode where all valid frames are copied to memory
Supports physical layer management through MDIO interface
10.14 Serial Peripheral Interface
Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
Connection to PDC channel optimizes data transfers
– One channel for the receiver, one channel for the transmitter
– Next buffer support
10.15 Two-wire Interface
Compatibility with standard two-wire serial memory
One, two or three bytes for slave address
Sequential Read/Write operations
10.16 USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
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