参数资料
型号: AT91SAM7S32-AU-001
厂商: Atmel
文件页数: 8/50页
文件大小: 0K
描述: IC ARM7 MCU 32BIT 32K 48LQFP
标准包装: 250
系列: SAM7S
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: I²C,SPI,SSC,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 21
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
配用: AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
其它名称: AT91SAM7S32-AU001
16
SAM7S Series [DATASHEET]
6175KS–ATARM–25-Oct-12
7.
Processor and Architecture
7.1
ARM7TDMI Processor
RISC processor based on ARMv4T Von Neumann architecture
Runs at up to 55 MHz, providing 0.9 MIPS/MHz
Two instruction sets
ARM high-performance 32-bit instruction set
Thumb high code density 16-bit instruction set
Three-stage pipeline architecture
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
7.2
Debug and Test Features
Integrated EmbeddedICE (embedded in-circuit emulator)
Two watchpoint units
Test access port accessible through a JTAG protocol
Debug communication channel
Debug Unit
Two-pin UART
Debug communication channel interrupt handling
Chip ID Register
IEEE1149.1 JTAG Boundary-scan on all digital pins
7.3
Memory Controller
Bus Arbiter
Handles requests from the ARM7TDMI and the Peripheral DMA Controller
Address decoder provides selection signals for
Three internal 1 Mbyte memory areas
One 256 Mbyte embedded peripheral area
Abort Status Registers
Source, Type and all parameters of the access leading to an abort are saved
Facilitates debug by detection of bad pointers
Misalignment Detector
Alignment checking of all data accesses
Abort generation in case of misalignment
Remap Command
Remaps the SRAM in place of the embedded non-volatile memory
Allows handling of dynamic exception vectors
Embedded Flash Controller
Embedded Flash interface, up to three programmable wait states
Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
Key-protected program, erase and lock/unlock sequencer
Single command for erasing, programming and locking operations
Interrupt generation in case of forbidden operation
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