参数资料
型号: AT91SAM7S32B-AU-999
厂商: Atmel
文件页数: 106/165页
文件大小: 0K
描述: IC MCU ARM7 32KB FLASH 48LQFP
产品培训模块: MCU Product Line Introduction
标准包装: 2,000
系列: SAM7S
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: I²C,SPI,SSC,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 21
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 带卷 (TR)
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
45
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
11.2.6
Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Branch instructions
Data processing instructions
Load and Store instructions
Load and Store Multiple instructions
Exception-generating instruction
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as
R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM
Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions
allow limited access to the ARM registers 8 to 15.
Table 11-3 gives the Thumb instruction mnemonic list.
AND
Logical AND
TEQ
Test Equivalence
EOR
Logical Exclusive OR
BIC
Bit Clear
MUL
Multiply
ORR
Logical (inclusive) OR
SMULL
Sign Long Multiply
MLA
Multiply Accumulate
SMLAL
Signed Long Multiply Accumulate
UMULL
Unsigned Long Multiply
MSR
Move to Status Register
UMLAL
Unsigned Long Multiply Accumulate
B
Branch
MRS
Move From Status Register
BX
Branch and Exchange
BL
Branch and Link
LDR
Load Word
SWI
Software Interrupt
LDRSH
Load Signed Halfword
STR
Store Word
LDRSB
Load Signed Byte
STRH
Store Half Word
LDRH
Load Half Word
STRB
Store Byte
LDRB
Load Byte
STRBT
Store Register Byte with Translation
LDRBT
Load Register Byte with Translation
STRT
Store Register with Translation
LDRT
Load Register with Translation
STM
Store Multiple
LDM
Load Multiple
SWPB
Swap Byte
SWP
Swap Word
MRC
Move From Coprocessor
MCR
Move To Coprocessor
STC
Store From Coprocessor
LDC
Load To Coprocessor
Table 11-2.
ARM Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
Table 11-3.
Thumb Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
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