参数资料
型号: AT91SAM7SE256-CU-999
厂商: Atmel
文件页数: 7/47页
文件大小: 0K
描述: IC MCU ARM7 256KB FLASH 144LFBGA
产品培训模块: MCU Product Line Introduction
标准包装: 3,000
系列: SAM7SE
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: EBI/EMI,I²C,SPI,SSC,UART/USART,USB
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 88
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LFBGA
包装: 带卷 (TR)
配用: AT91SAM7SE-EK-ND - EVAL BOARD FOR AT91SAM7SE
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
15
6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
6.
/O Lines Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up
resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 k
Ω.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on
JTAGSEL, it should be tied externally to GND if boundary scan is not used, or put in place an
external low value resistor (such as 1 k
Ω) .
6.2
Test Pin
Th e T S T p i n is used f o r ma nu f a ct ur in g t e st o r f a st pr og ra mmi ng mod e of t h e
SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resis-
tor of about 15 k
Ω to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to
GND if the FFPI is not used, or put in place an external low value resistor (such as 1 k
Ω) .
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3
Reset Pin
The NRST pin is bidirectional with an open-drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset
all the components of the system.
An external power-on reset can drive this pin during the start-up instead of using the internal
power-on reset circuit.
The NRST pin integrates a permanent pull-up of about 100 k
Ω resistor to VDDIO.
This pin has Schmitt trigger input.
6.4
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 k
Ω to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it should be tied exter-
nally to GND, which prevents erasing the Flash from the application, or put in place an external
low value resistor (such as 1 k
Ω) .
This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to
high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high
during more than 220 ms to perform the re-initialization of the Flash.
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