参数资料
型号: AT91SAM7X128C-CU
厂商: Atmel
文件页数: 28/44页
文件大小: 0K
描述: IC MCU 32BIT 128KB FLSH 100TFBGA
产品培训模块: SAM9 MPU Boot Solutions & Application Deployment
AT91SAM7X and SAM7XC Flash-based Microcontrollers
MCU Product Line Introduction
标准包装: 260
系列: SAM7X
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 55MHz
连通性: CAN,以太网,I²C,SPI,SSC,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 62
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 1.95 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
34
6120GS–ATARM–07-Apr-11
SAM7X512/256/128 Summary
10.6
Ethernet MAC
DMA Master on Receive and Transmit Channels
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s operation
Full- and half-duplex operation
Statistics Counter Registers
MII/RMII interface to the physical layer
Interrupt generation to signal receive and transmit completion
28-byte transmit FIFO and 28-byte receive FIFO
Automatic pad and CRC generation on transmitted frames
Automatic discard of frames received with errors
Address checking logic supports up to four specific 48-bit addresses
Support Promiscuous Mode where all valid received frames are copied to memory
Hash matching of unicast and multicast destination addresses
Physical layer management through MDIO interface
Half-duplex flow control by forcing collisions on incoming frames
Full-duplex flow control with recognition of incoming pause frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged
frames
Multiple buffers per receive and transmit frame
Jumbo frames up to 10240 bytes supported
10.7
Serial Peripheral Interface
Supports communication with external serial devices
– Four chip selects with external decoder allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays per chip select, between consecutive transfers and
between clock and data
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Maximum frequency at up to Master Clock
10.8
Two-wire Interface
Master Mode only
Compatibility with I
2C compatible devices (refer to the TWI section of the datasheet)
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