参数资料
型号: 97SD3248RPMI
厂商: MAXWELL TECHNOLOGIES
元件分类: DRAM
英文描述: 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
封装: STACK, QFP-132
文件页数: 4/40页
文件大小: 758K
代理商: 97SD3248RPMI
97SD3248
M
em
o
ry
12
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
Function Truth Table
The following function table shows the operations that are performed when each command is issued in each
mode of the SDRAM.
The following table assumes that CKE is High.
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION
Precharge
H
x
DESL
Enter IDLE after t
RP
L
H
x
NOP
Enter IDLE after t
RP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL1
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL1
L
H
BA, RA
ACTV
ILLEGAL1
L
H
L
BA, A10
PRE, PALL
NOP2
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
Idle
H
x
DESL
NOP
LH
H
x
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL3
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL3
L
H
BA, RA
ACTV
Bank and row active
L
H
L
BA, A10
PRE, PALL
NOP
L
H
x
REF, SELF
Refresh
L
MODE
MRS
Mode register set
Row active
H
x
DESL
NOP
LH
H
x
NOP
L
H
L
H
BA, CA, A10
READ/READ A
Begin read
L
H
L
BA, CA, A10
WRIT/WRIT A
Begin write
L
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank4
L
H
L
BA, A10
PRE, PALL
Precharge
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
相关PDF资料
PDF描述
97SD3248RPMK 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
97U870AKIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
97U870AH 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AHIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AKT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
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