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参数资料
| 型号： | AT91SAM9N12-EK |
| 厂商： | Atmel |
| 文件页数： | 10/27页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR SAM9N12 |
| 设计资源： | AT91SAM9N12-EK Design & Mfg Files SAM9N12-EK Design & Mfg File Information |
| 标准包装： | 1 |
| 类型： | MCU |
| 适用于相关产品： | ATSAM9N12 |
| 所含物品： | 板 |
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18
11096AS–ATARM–4-Oct-11
SAM9N12
6.1
Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to
6 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second
level of decoding provides 1Mbyte of internal memory area. The bank 15 is reserved for the
peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
6.2
Embedded Memories
6.2.1
Internal SRAM
The SAM9N12 embeds a total of 32 Kbytes high-speed SRAM.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
6.2.2
Internal ROM
The SAM9N12 contains the bootloader and specific tables used to compute SLC and MLC
NAND Flash ECC.
The ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1)
after the reset and before the Remap Command.
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